The present invention relates to a program controlled digital computer, and more particularly to a vector processor which is suitable for carrying out a vector operation at a high speed.
A vector processor has been used for high speed calculation, such as a large scale matrix calculation of the type frequently called for in scientific and technical calculations. In such a vector processor, an operation such as that shown in the following FORTRAN instruction is vector-processed at a high speed.
______________________________________ DO 10 i=1, N IF (A(i).EQ. 3) THEN B(i)=1 10 CONTINUE ______________________________________
Namely, (A(i).i=1, N) is defined as a vector A and (B(i).i=1, N) is defined as a vector B. When a vector element (A(i)) of the vector A is equal to 3, "1" is substituted for the corresponding vector element (B(i)) of the vector B. The vector processor carries out such a vector operation at a high speed by using a vector processing technique.
However, when a part of a structure of the following PL/I instruction is to be compared with contents of FLAGS 1 and 2, the process is very complex.
______________________________________ DCL 1 FLAG (50), 2 FLAG 1 BIT (1), 2 * BIT (30), 2 FLAG 2 BIT (1); DO i=1 TO 50; IF FLAG 1 (i) = `1`B & FLAG 2 (i) = `1`B THEN A(i) = B(i); END; ______________________________________
If this PL/I instruction is executed by using the above vector processing technique, the following vector instruction objects are generated.
______________________________________ VL VR0, FLAG VEO VR4, VR0, SR0 VCEQ VMR0, VR4, SR4 VL VR8, B VSTN VR8, A ______________________________________
Of those fine instructions, the upper three correspond to the IF clause and the lower two correspond to the THEN clause.
The abbreviations of the above instructions are explained below.
______________________________________ VL: VECTOR LOAD, VEO: VECTOR-ELEMENTWISE OR, VCEQ: VECTOR COMPARE EQUAL, VSTN: VECTOR STORE NEGATIVE MASK VRi: i-th vector register SRi: i-th scalar register VMRi: i-th vector mask register ______________________________________
A 4-byte hexadecimal number `7FFFFFFE` is preset in SR0, and a 4-byte hexadecimal number `FFFFFFFF` is preset in SR4.
DO i=1 TO 50 in the PL/I instruction is considered as one vector column, and the decision for the next IF clause is carried out by a VL instruction, VE0 instruction and VCEQ instruction. In accordance with the result thereof, a substitution of A(i)=B(i); described by the THEN clause is stored in an array A, while all elements of an array B are loaded by the VL instruction, and data satisfying the condition in the If sentence are is selected by a masked VSTN instruction.
However, as seen from the above example, three vector registers VR0, VR4, VR8 in the DCL clause, two scalar registers SR0 and SR4 in the IF clause and one mask register VMR0 in the THEN clause are occupied for one decision by the program. This impedes effective utilization of registers. The instruction sequence also takes two steps only for a decision. These circumstances makes it difficult to vectorize for a structured programming language, such as PL/I.
Such a technique is disclosed in JP-A-60-15772.
Such a vector processor is described in "Hitach Super Computer S-810 Array Processor System" by Toshihiko Okada et al, Elsevier Science Publishers B.V. (North-Holland), 1986, pages 113-136.
The prior technique does not pay attention to bit determination in a structure as frequently used in the structured programming language represented by PL/I and has problems in that the instruction sequence is complex and many register resources are used.
A reason therefor is that the vector processor is usually utilized for speed-up of processing of a language for carrying out a numeric operation represented by FORTRAN and it is not utilized for speed-up of PL/I which requires complex logical operations. This is because a large capacity array for a large scale matrix operation which is a base of vectorization is easy to handle in FORTRAN. However, in recent years, the large capacity array is required even in PL/I in a field of a data base and the vectorization of the bit determination for a structure is becoming feasible.